1. Field of the Invention
The present invention relates to a display device, and more particularly to a display device which includes a drive circuit having a CMOS shift register which is constituted of a CMOS circuit.
2. Description of the Related Art
In general, in an active matrix liquid crystal display device which uses thin film transistors (TFT: Thin Film Transistor) as active elements, for example, a shift register circuit is used for sequentially applying a selective scanning voltage to scanning lines.
As the shift register circuit, there have been known a CMOS shift register which is constituted of a CMOS (Complementary Metal Oxide Semiconductor) (see following Patent Document 1, Patent Document 2 below) and an nMOS single-channel shift register which is constituted of an nMOS single-channel transistor (see Patent Document 3 below).
FIG. 14 is a circuit diagram showing a unit circuit of a conventional CMOS shift register which is the circuit constitution described in the above-mentioned Patent Document 1 and Patent Document 2.
The unit circuit shown in FIG. 14 includes a clocked inverter (INV1) which inverts an input signal (IN), an inverter (INV2) which re-inverts an inverted signal of the input signal (IN), and a clocked inverter (INV3) which feedbacks a re-inverted signal of the input signal (IN) to an input of the inverter (INV2).
Then, an output of the inverter (INV2) becomes a transfer output (TRN). Further, the input signal (IN) and the transfer output (TR) are inputted to a NAND circuit (NAND). An output signal of the NAND circuit (NAND) is inverted by an inverter (INV4) thus generating a scanning circuit output (OT).
Here, the clocked inverter (INV1) in an odd-numbered-row unit circuit inverts the input signal when a clock (CLK) assumes a High level (inverting clock (CLKB) being at a Low level), and the clocked inverter (INV3) in unit circuit in the same row inverts the input signal when the clock (CLK) assumes a Low level ((inverting clock (CLKB) being at a High level).
On the other hand, in the clocked inverter (INV1, INV3) in an even-numbered-row unit circuit, the relationship with the clock signal which inverts the input signal is opposite to the relationship with the clock signal in the odd-numbered-row unit circuit.
Here, there have been known following related art which is relevant to the present invention.
Patent Document 1: JP-A-2000-227784
Patent Document 2: JP-A-10-199284
Patent Document 3: JP-A-2002-215118